Semiconductor device manufacturing method, semiconductor device, and wiring board

ABSTRACT

A semiconductor device manufacturing method includes (a) bonding a first surface of a metal plate to a substrate, (b) forming a plurality of metal posts that are arranged in vertical and lateral directions in a plan view and include a first metal post and a second metal post, by partially etching the metal plate bonded to the substrate from a second surface of the metal plate, (c) fixing an integrated circuit (IC) element to the second surface of the first metal post, (d) coupling the second metal post and a pad terminal of the integrated circuit element via a conductive material, (e) resin-sealing the integrated circuit element, the metal posts, and the conductive material by providing a resin onto the substrate, and (f) removing the substrate from the resin and the first surfaces of the metal posts sealed using the resin.

The entire disclosure of Japanese Patent Application No.2007-012741,filed Jan. 23, 2007 is expressly incorporated by reference herein.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device manufacturingmethod, a semiconductor device, and a wiring board.

2. Related Art

Semiconductor packages are broadly categorized into peripheral typepackages whose outside terminals are disposed in the periphery of apackage and area type packages whose outside terminals are disposedbelow the undersurface of a package. Peripheral type packages arerepresented by a dual inline package (DIP), a small outline package(SOP), and a quad flat package (QFP) as shown in FIGS. 21A to 21C. Forexample, in FIG. 21D, a peripheral type package is manufactured bymounting an integrate circuit (IC) element 210 on a die pad 201 servingas a chip mounting part, then coupling an electrode of the IC element210 and leads 203 of the a lead frame via gold wires or the like, andresin-sealing all these components except for portions of the outerperipheries of the leads 203. Portions of the leads 203 inside the resinpackage are called “inside terminals” and portions of the leads 203outside the resin package are called “outside terminals.”

Area type packages are represented by ball grid array (BGA) packages asshown in FIGS. 22A, 22B, 23A, and 23B. For example, in these drawings,an area type package is manufactured by mounting the IC element 210 onthe substrate 211, electrically coupling the substrate 211 and the ICelement 210 via a gold wire, solder, or a gold bump, and resin-sealingthe IC element 210 and the like. A BGA package in which the substrate211 and the IC element 210 are coupled via a gold wire 213, as shown inFIGS. 22A and 22B, is also called a “gold wire BGA package.” A BGApackage in which the substrate 211 and the IC element 210 are coupledvia a bump 223, as shown in FIGS. 23A and 23B, is also called a “bumpBGA package.” Among bump BGA packages is a type of bump BGA package thatis not resin-sealed. The outside terminals of an area type package arenot leads and, for example in FIGS. 23A to 23B, are electrodes (orsolder balls) 225 mounted on the back of the substrate 211.

In recent years, a package is also manufactured, for example in FIG. 24Ato 241, by forming cylindrical terminals 233 and a die pad 235 on ametal plate 231 by electrical plating, then mounting the IC element 210on the die pad 235, coupling the IC element 210 and the terminals 233via the gold wires 213, then resin-sealing these components, removingthe metal plate 231 from a resin molding 236, and cutting the resinmolding 236 into individual products.

More specifically, in FIGS. 24A and 24B, first, a resist is applied ontothe metal plate 231, and subjected to exposure and development so as toform a resist pattern 237. Next, as shown in FIG. 24C, for example,copper is formed on the surface of the metal plate 231 exposed frombelow the resist pattern 237 by electrical plating so as to form thecylindrical terminals 233 and the die pad 235. Then, as shown in FIG.24D, the resist pattern is eliminated. Next, as shown in FIG. 24E, theIC element 210 is mounted on the die pad 235 formed by electricalplating, and wire-bonded to the terminals 233. Then, as shown in FIG.24F, the IC element 210, the gold wires 213, and the like areresin-sealed. Next, as shown in FIG. 24G, the metal plate 231 is removedfrom the resin molding 236. Then, as shown in FIGS. 24H and 241, marginsare cut away from the resin molding 236 so as to complete the package.

Disclosed in JP-A-02-240940 is a technology that completes a peripheraltype package by half-etching one surface of a supporter of a flat leadframe, then mounting an IC element on a die pad of the lead frame,subsequently wire-bonding and resin-sealing these components, and thengrinding the other surface of the supporter to eliminate the supporter.Disclosed in JP-A-2004-281486 is a technology that attempts to enhancethe general versatility of an area type package by disposing wiring fromthe center of a substrate outward in all directions in a plan view.

The related art examples, that is, peripheral type packages, area typepackages, the package shown in FIGS. 24A to 24I, and the packagedescribed in JP-A-02-240940 all require a substrate serving as amounting surface for an IC element, such as a die pad or an interposer,as well as requires a dedicated lead frame or substrate, or a dedicatedphotomask (to form a cylindrical terminal) according to the size of theIC element or the number of external outputs from the IC element (thatis, the number of leads or balls). In particular, if small batches of avariety of products are manufactured, various lead frames or substrates,or various photomasks must be possessed. This prevents a reduction inmanufacturing cost.

Also, in JP-A-02-240940, area type packages corresponding to variouschip sizes are achieved by disposing wiring from the center of asubstrate outward in all directions. However, this technology requiresthat the pad terminal of the IC element be disposed so as to alwaysoverlap the wiring extending from the center of the substrate outward inall directions in a plan view; therefore, flexibility in design isreduced with respect to the layout of the pad terminal. That is, thegeneral versatility of the package is enhanced, while more limitationsare imposed on the IC element.

SUMMARY

An advantage of the invention is to provide a semiconductor devicemanufacturing method, a semiconductor device, and a wiring board thateach allow commonality of the specifications of a wiring board formounting an IC element, without imposing more limitations on the ICelement.

According to a first aspect of the invention, a semiconductor devicemanufacturing method includes (a) bonding a first surface of a metalplate to a substrate, (b) forming a plurality of metal posts that arearranged in vertical and lateral directions in a plan view and include afirst metal post and a second metal post, by partially etching the metalplate bonded to the substrate from a second surface of the metal plate,(c) fixing an integrated circuit element to the second surface of thefirst metal post, (d) coupling the second metal post and a pad terminalof the integrated circuit element via a conductive material, (e)resin-sealing the integrated circuit element, the metal posts, and theconductive material by providing a resin onto the substrate, and (f)removing the substrate from the resin and the first surfaces of themetal posts sealed using the resin.

Here, the “metal plate” refers to, e.g., a copper plate, the “substrate”refers to, e.g., a glass substrate, the “conductive material” refers to,e.g., a gold wire, and the “resin” refers to, e.g., a thermosettingepoxy resin.

According to the semiconductor device manufacturing method according tothe first aspect of the invention, the multiple metal posts are used asdie pads for mounting an integrated circuit element or as outsideterminals of the integrated circuit element. Specifically, the multiplemetal posts are selectively used as die pads or outside terminalsaccording to the shape and size of an IC-fixing region that arearbitrarily set. In other words, the metal posts can become any of diepads and outside terminals. The first metal post is used as a die pad,and the second metal post is used as an outside terminal.

Therefore, there is no need for preparing dedicated die pads or a leadframe, or a dedicated substrate (interposer, etc.) for each integratedcircuit element type in order to assemble a semiconductor device. Thisallows commonality of the specifications of a wiring board used to mountan element and used as an outside terminal without limiting the layout(disposition) of the pad terminals with respect to various types ofintegrated circuit elements. This helps reduce the manufacturing cost ofthe semiconductor device.

The semiconductor device manufacturing method according to the firstaspect of the invention preferably further includes (g) forming themetal posts partway by partially half-etching the metal plate from thefirst surface prior to the bonding of the first surface of the metalplate. In the forming of the plurality of the metal posts, the metalplate is preferably penetrated by etching the half-etched metal platefrom the second surface.

According to this method, the metal posts are easily processed into anarbitrary shape. For example, as shown in FIG. 8A, the metal posts canbe shaped to be thick in their upper and lower ports and thin in theircentral part in a sectional view. Also, as shown in FIGS. 8B and 8C, themetal posts can be each shaped into a trapezoid or an inverted trapezoidin a sectional view.

The semiconductor device manufacturing method according to the firstaspect of the invention preferably further includes (h) forming a platedlayer for solder joint on the first surface of the metal plate on whichthe metal posts are formed partway, prior to the bonding of the firstsurface of the metal plate. Here, the “plated layer for solder joint”refers to, e.g., a silver (Ag) thin film or a palladium (Pd) thin film.

According to this method, the plated layer is formed on the outerperipheries of the metal posts adjacent to the first surfaces thereof.Therefore, if the first surfaces of the metal posts are soldered to, forexample, a motherboard or the like, solder can extensively be placed onfrom the first surfaces of the posts to the outer peripheries of themetal posts adjacent to the first surfaces thereof. This allows themetal posts and the motherboard to be bonded together with high bondingstrength.

In the semiconductor device manufacturing method according to the firstaspect of the invention, in the fixing of the integrated circuit, theintegrated circuit element is preferably mounted in a plurality of unitsside by side in a plan view on the second surface of the first metalpost. In the coupling the second metal post and a pad terminal of theintegrated circuit element, the pad terminals of the integrated circuitelements and the second metal post are preferably coupled via theconductive material. In the resin-sealing of the integrated circuitelement, the integrated circuit elements, the metal posts, and theconductive material are preferably collectively sealed using the resin.The semiconductor device manufacturing method preferably furtherincludes (i) dicing the resin so that the integrated circuit elementsare contained in a resin package, after the resin-sealing of theintegrated circuit element.

According to this method, a so-called “multi-chip module” (MCM) in whichmultiple integrated circuit elements are contained in the state of barechips in a package is provided.

In the semiconductor device manufacturing method according to the firstaspect of the invention, the second metal post preferably includes athird metal post and a fourth metal post. The conductive materialpreferably includes a first conductive material and a second conductivematerial. In the coupling the second metal post and a pad terminal ofthe integrated circuit element, the pad terminal of the integratedcircuit element and the third metal post are preferably coupled via thefirst conductive material and the third metal post and the fourth metalpost are preferably coupled via the second conductive material.

According to this method, the positions of the outside terminals of thesemiconductor device are substantially changed without changing thelayout of the metal posts. As a result, the general versatility of thewiring board is further enhanced.

In the semiconductor device manufacturing method according to the firstaspect of the invention, in the forming of the plurality of the metalposts, the metal posts are preferably all formed to have identicalshapes and identical sizes.

According to a second aspect of the invention, a semiconductor deviceincludes: a plurality of metal posts each having a first surface and asecond surface facing a side opposite to the first surface; the metalposts arranged in vertical and lateral directions in a plan view, themetal posts including a first metal post and a second metal post; anintegrated circuit element fixed to the first surface of the first metalpost; a conductive material, the conductive material coupling the firstsurface of the second metal post and a pad terminal of the integratedcircuit element; and a resin sealing the metal posts, the integratedcircuit element, and the conductive material. The second surfaces of themetal posts are exposed from the resin.

In the semiconductor device according to the second aspect of theinvention, the first and second posts are preferably all formed to haveidentical shapes and identical sizes.

In the semiconductor device according to the second aspect of theinvention, a plated layer for solder joint is preferably formed on thesecond surfaces of the metal posts.

Here, among the reliability tests of a semiconductor device is a test inwhich it is checked whether no abnormality has occurred in a resinpackage when the resin package undergoes heating with the package forcedto absorb water. One of typical failed modes detected in this test is arupture of the resin package. This is a phenomenon in which when a resinpackage undergoes heating, water vapor gradually accumulates in theresin package, thereby increasing the pressure, and in which the resinpackage ruptures from inside when it can no longer endure the increasedpressure. Conceivably, this phenomenon occurs because water absorbed inthe resin package flocculates around the interface between the metalcomponent (that is, the die pad or outside terminal) and the resin andthus the vapor pressure is intensively increased around the interface.

According to the semiconductor device according to the second aspect ofthe invention, the metal components are not concentrated around onelocation unlike a related art die pad. The metal posts serving as diepads or as outside terminals are disposed in a distributed manner in theresin package; therefore, positions where water flocculates aredistributed, whereby concentration of the vapor pressure is reduced.This suppresses a rapture of the resin package in the above-mentionedreliability test, thereby enhancing the reliability of the semiconductordevice.

According to a third aspect of the invention, a wiring board includes asubstrate and a plurality of metal posts arranged in vertical andlateral directions in a plan view on the substrate. The substrate andthe metal posts are bonded together via a type of adhesive that losesadhesion force thereof if the adhesive is subjected to a predeterminedprocess. Here, the “type of adhesive that loses adhesion force thereofif the adhesive is subjected to a predetermined process” refers to, forexample, an ultraviolet curing adhesive (UV adhesive) that losesadhesion force thereof if an ultraviolet ray (UV) is applied to theadhesive.

According to the wiring board according to the third aspect of theinvention, the semiconductor device according to the second aspect ofthe invention is manufactured by fixing an integrated circuit element tothe metal posts disposed in an IC-fixing region, coupling the metalposts disposed in a region other than the IC-fixing region and the padterminal of the integrated circuit element via the conductive material,resin-sealing the integrated circuit element, the multiple metal posts,and the conductive material by providing the resin onto the substrate,and then removing the substrate from the resin and the metal posts. As aresult, there is no need for preparing dedicated die pads or a leadframe, or a dedicated substrate (interposer, etc.) for each integratedcircuit element type, allowing the commonality of the specifications ofa wiring board.

In the wiring board according to the third aspect of the invention, themetal posts are preferably all formed to have identical shapes andidentical sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings, wherein like numbers reference like elements.

FIGS. 1A and 1B are drawings showing a method for manufacturing a wiringboard 50.

FIGS. 2A and 2B are drawings showing the method for manufacturing thewiring board 50.

FIG. 3 is a drawing showing the method for manufacturing the wiringboard 50.

FIGS. 4A and 4B are drawings showing the method for manufacturing thewiring board 50.

FIGS. 5A to 5C are drawings showing the method for manufacturing thewiring board 50.

FIGS. 6A to 6C are drawings showing the method for manufacturing thewiring board 50.

FIG. 7 is a drawing showing a configuration example of the wiring board50.

FIGS. 8A to 8C are drawings showing examples of the sectional shape of apost 40.

FIGS. 9A to 9C are drawings showing a method for manufacturing asemiconductor device 100.

FIGS. 10A to 10C are drawings showing the method for manufacturing thesemiconductor device 100.

FIGS. 11A to 11C are drawings showing the method for manufacturing thesemiconductor device 100.

FIGS. 12A to 12C are drawings showing the method for manufacturing thesemiconductor device 100.

FIGS. 13A to 13C are drawings showing the method for manufacturing thesemiconductor device 100.

FIGS. 14A to 14C are drawings showing an example configuration of thesemiconductor device 100.

FIGS. 15A and 15B are drawings showing example configurations of thesemiconductor device 100.

FIGS. 16A and 16B are drawings showing examples in which the posts 40are disposed in the form of a grid.

FIGS. 17A and 17B are drawings showing an example configuration of thesemiconductor device 100.

FIG. 18 is a drawing showing an example in which the posts 40 aredisposed in a staggered manner.

FIGS. 19A to 19C are drawings showing another method for manufacturingthe semiconductor device 100.

FIGS. 20A and 20B are drawings showing an example configuration of asemiconductor device 200.

FIGS. 21A to 21D are drawings showing related art examples.

FIGS. 22A and 22B are drawings showing related art examples.

FIGS. 23A and 23B are drawings showing related art examples.

FIGS. 24A to 24I are drawings showing a related art example.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the invention will now be described with reference to theaccompanying drawings.

(1) First Embodiment

FIGS. 1A to 6C are drawings showing a method for manufacturing a wiringboard 50 according to a first embodiment of the invention. Morespecifically, FIGS. 1A, 2A, and 4A are bottom views, and FIGS. 1B, 2B,and 4B are end views taken along lines X1-X′1, X2-X′2, and X4-X′4 ofFIGS. 1A, 2A, and 4A, respectively. FIGS. 6A to 6C are end views showingmanufacturing processes following that shown in FIG. 5C.

First, a copper plate 1 as shown in FIGS. 1A and 1B is prepared. It issufficient that the vertical and lateral sizes of the copper plate 1 ina plan view are larger than those of the package shape of asemiconductor device to be made of the copper plate 1. The thickness hof the copper plate 1 is, for example, about 0.10 to 0.30 mm. Next, asshown in FIGS. 2A and 2B, the resist 3 entirely covers the top surfaceof the copper plate 1, and a resist pattern 5 is formed on theundersurface of the copper plate 1 so that the undersurface is partiallyexposed. As shown in FIGS. 2A and 2B, for example, the resist patterns 5each take the shape of a regular circle, and has a center-to-centerinterval (that is, pitch) of about 0.5 to 1.0 mm and a diameter φ ofabout 0.2 to 0.3 mm.

Next, as shown in FIG. 3, the undersurface of the copper plate 1 ishalf-etched (that is, the copper plate 1 is etched partway in thethickness direction) with the resist patterns 5 as masks so as to formrecesses 7 on the undersurface. For example, a ferric chloride solutionis used to etch the copper plate 1. Subsequently, as shown in FIGS. 4Aand 4B, the top and under surfaces of the copper plate 1 are plated witha metal thin film 9 made of silver (Ag) or palladium (Pd) or the like.This plating with the metal thin film 9 may be performed before thecopper plate 1 is etched.

Before or after or simultaneously with such plating, a substrate 21 asshown in FIG. 5A is prepared and its top surface is coated with anadhesive, as shown in FIG. 5B. The substrate 21 is, for example, a glasssubstrate. The adhesive 23 is, for example, a solder resist, anultraviolet curing adhesive (that is, UV adhesive), a thermosettingadhesive, or the like. Then, as shown in FIG. 5C, the undersurface ofthe plated copper plate 21 is pressed against the top surface of thesubstrate 21 coated with the adhesive 23 so that these surfaces adhereto each other.

Next, as shown in FIG. 6A, resist patterns 31 are formed on the topsurface of the copper plate 1 so as to cover the top surface in a mannerthat apertures are provided in regions on the top surface where therecesses 7 are formed in a plan view. Then, as shown in FIG. 6B, thecopper plate 1 is etched with the resist patterns 31 as masks until itis penetrated so that multiple cylindrical electrodes (hereafterreferred to as “posts”) 40 are formed. After the multiple posts 40 areformed of the copper plate 1, the resist patterns are eliminated fromthe top surfaces of the posts 40, as shown in FIG. 6C. Thus, the wiringboard 50 is completed. As shown in FIG. 7, a great number of posts 40,which are formed of the copper plate 1, are formed on the substrate.These posts have identical shapes and sizes and are disposed at equalintervals in the vertical and lateral directions in a plan view.

FIGS. 8A to 8C are drawings showing examples of the sectional shape ofthe posts 40. As shown in FIGS. 8A to 8C, respective diameters φ1 and φ2of the top and under surfaces of the posts 40 formed according to theabove-mentioned manufacturing method may have identical sizes, or the φlmay be smaller than the φ2 or the φ1 may be larger than φ2. Each casehas an advantage.

In order to form each post 40 such that φ1<φ2 as shown in FIG. 8A, it issufficient to etch the copper plate 1 from its top and under surfacesusing the resist patterns 5 and 31 (see FIGS. 2A and 2B and 6A to 6C)whose masked regions (that is, covered regions) have identical shapesand sizes. In this case, the resist patterns 5 and 31 are formed usingan identical type of photomasks; therefore, the manufacturing cost ofthe wiring board 50 is reduced compared with a case where differenttypes of photomasks are used. If each post 40 is formed such that φ1<φ2as shown in FIG. 8B, the area where the substrate 21 and each post 40adhere to each other is increased, whereby the posture of each post 40is stabilized. This makes it less likely for the posts 40 to topple overduring an IC element mounting process (that is, die attach process) or aresin-sealing process to be discussed later. If each post 40 is formedsuch that φ1>φ2 as shown in FIG. 8C, clearances between adjacent postsin the vicinity of the substrate 21 are increased. This makes itrelatively easy to fill the clearances with resin.

In order to form each post 40 such that φ1<φ2 as shown in FIG. 8B, it issufficient that the masked regions of the resist patterns 5 formed onthe undersurface of the copper plate 1 and those of the resist patterns31 formed on the top surface of the copper plate 1 are made intoconcentric circles and that the masked regions of the resist patterns 5are made larger than those of the resist patterns 31. In other words, itis sufficient to make the aperture area of each resist pattern 5 smallerthan that of each resist pattern 31. Thus, the top surface of the copperplate 1 is etched more widely than the undersurface thereof so thatφ1<φ2.

In order to form each post 40 such that φ1=φ2 as shown in FIG. 8C, it issufficient that the masked regions of the resist patterns 5 formed onthe undersurface of the copper plate 1 and those of the resist patterns31 formed on the top surface of the copper plate 1 are made intoconcentric circles and that the masked regions of the resist patterns 5are made smaller than those of the resist patterns 31. Thus, theundersurface of the copper plate 1 is etched more widely than the topsurface thereof so that φ1>φ2.

Further, for example, the outside shape of the copper plate 1 ispreferably used as marks so as to register photomasks in the respectiveprocesses of forming the resist patterns 5 and 31 on the copper plate 1by photolithography. This method allows the resist patterns 5 and 31 tobe formed on the copper plate 1 with high registration accuracy, therebysufficiently reducing the amount of misalignment between the resistpatterns 5 and 31.

A method for mounting a bare IC element on the wiring board 50 tomanufacture the semiconductor device 100 will now be described.

FIGS. 9A to 13B are drawings showing a method for manufacturing thesemiconductor device 100 according to the first embodiment. Morespecifically, FIGS. 9A to 13A are plan views showing a case where thechip size of each IC element 51 is 2 mm per side, and FIGS. 9B to 13Bare plan views showing a case where the chip size of each IC element 51is 1 mm per side. FIGS. 9C to 13C are end views taken along lines Y9-Y′9to Y13-Y′13 of FIGS. 9B to 13B.

First, as shown in FIGS. 9A to 9C, an adhesive (not shown) is applied tothe top surfaces of the posts 40 located in IC-fixing regions, and theback surface of each IC element 51 is brought into contact with the topsurfaces of the posts 40 and fixed (die attach process). For example,the adhesive used here is a thermosetting paste or sheet. Next, as shownin FIG. 10A to 10C, the top surfaces of the posts 40 located in regions(that is, regions not located directly below the IC elements 51) otherthan the IC-fixing regions and the pad terminals of the IC elements 51are coupled via, for example, the gold wires 53 (wire bonding process).Then, as shown in FIGS. 11A to 11C, the entire region above thesubstrate 21, including the IC elements 51, the gold wires 53, and theposts 40, is sealed using a resin 61 (resin-sealing process). Forexample, the resin 61 is a thermosetting epoxy resin, or the like. Sincethe substrate 21 is made of a material having a relatively small thermalexpansion coefficient, such as a glass substrate, as described above,the substrate 21 hardly expands in the vertical and lateral directionsin a plan view even if heat of the order of 200° C. is applied theretoduring the resin-sealing process. Therefore, the intervals betweenadjacent posts 40 are maintained constant even during the resin-sealingprocess.

Subsequently, as shown in FIGS. 12A to 12C, a resin 61 containing the ICelements 51 is removed from the substrate. If an ultraviolet curingadhesive has been used as the adhesive 23, the resin 61 may be removedfrom the substrate after ultraviolet rays are applied to the surfaceswhere the posts 40 and the substrate adhere to each other so as toreduce the adhesion force of the adhesive. Or the resin 61 may beremoved from the substrate by only applying mechanical force to theresin 61. The adhesive may be left on the resin or on the substrateafter the removal. FIG. 15A shows a case where the adhesive 23 is lefton the resin 61, and FIG. 15B shows a case where the adhesive 23 isremoved together with the substrate. This embodiment may be any of whatare shown in FIGS. 15A and 15B. After the resin 61 is removed from thesubstrate, the metal thin film 9 is exposed from the removed surface ofthe resin 61.

Next, in FIGS. 12A to 12C, product marks (not shown) are put on the topsurface of the resin 61 (that is, the surface where no terminal isexposed), for example, using ink and a laser. Then, as shown in FIGS.13A to 13C, for example, an ultraviolet curing tape (UV tape) 63 iscontinuously affixed on the entire top surface of the resin 61. Then,the resin 61 is cut along the outside shapes of products using a dicingsaw (dicing process). In this dicing process, the resin 61 is dividedinto individual resin packages 62 and margins of the resin that nolonger become a product are cut away. For example, the resin is cutusing, as marks, the posts 40 exposed from the undersurface (that is,the surface from which terminals are exposed) of the resin 61.

Thus, as shown in FIGS. 14A to 14C, the semiconductor device 100including the IC element 51, the posts 40, the gold wires 53, and theresin package 62 for packaging these components is completed. The posts40 (that is, outside terminals) exposed from the resin package may beleft intact, or solder balls or the like may be mounted on the exposedsurfaces of the posts 40.

Table 1 shows one example of the applied chip size, the count of(external) terminals below a chip, the maximum count of outsideterminals, and the package size of the semiconductor device 100according to the first embodiment.

TABLE 1 Pitch Size of applied Terminal count Max. outside Package size(mm) chip (mm SQ) below chip terminal count (mm) 0.5 1 4 16 2.5 0.5 2 1636 3.5 0.5 3 36 64 4.5 0.5 4 64 100 5.5 0.5 5 100 144 6.5 0.5 6 144 1967.5 0.5 7 196 256 8.5

In Table 1, the “pitch” refers to the interval between adjacent posts,more specifically, the interval from the center of one post to thecenter of another post. As shown in Table 1 and FIG. 16A, the pitch is,for example, about 0.5 mm. The “size of applied chip” refers to the chipsize of an IC element sealed in a resin package (the shape of an ICelement in a plan view is, for example, a square).

The “max. outside terminal count” refers to the maximum count of theposts 40 to be resin-sealed by a resin package. The “package size”refers to the vertical or lateral length of a resin package in a planview (the shape of a resin package in a plan view is, for example, asquare). If the posts 40 are disposed systematically in the vertical andlateral directions in a plan view, more specifically, disposed at theintersections of a grid in a plan view (hereafter simply referred to as“disposed in the form of a grid) as shown in Table 1 and FIG. 16B, alarger area of an IC element-fixing region (that is, “IC-fixing region”)or a larger area of a region to be resin-sealed (that is, “region to besealed”) covers a larger number of posts 40.

As described above, according to the semiconductor device 100 accordingto this embodiment, the posts 40 are used as die pads for mounting theIC elements or as the outside terminals of the IC elements 51. Morespecifically, the posts 40 are selectively used as die pads or asoutside terminals according to the shapes and sizes of IC-fixing regionsthat are arbitrarily set. In other words, the posts 40 can become any ofdie pads and outside terminals. Therefore, unlike in related artexamples, there is no need for preparing dedicated die pads or a leadframe, or a dedicated substrate (interposer, etc.) for each type of ICelement 51 in order to assemble a semiconductor device. This allowscommonality of the specifications of the wiring board 50 used to mountan element and used as an outside terminal without limiting the layoutof the pad terminals with respect to various types of IC elements 51.This helps reduce the manufacturing cost of the semiconductor device.

Also, according to the above-mentioned manufacturing method, the metalthin film 9 is formed on the outer peripheries of the posts 40 adjacentto undersurfaces thereof, as shown in FIGS. 6A to 6C. Therefore, if theundersurfaces of the posts 40 are soldered to a motherboard or the like,solder can extensively be put on from the undersurfaces to the outerperipheries of the posts. This allows the posts 40 and the motherboardto be bonded together with high bonding strength.

Also, according to the semiconductor device according to thisembodiment, as shown in FIGS. 17A to 17C, the metal components are notconcentrated around one location unlike a related art die pad. The posts40 serving as die pads or as outside terminals are disposed in adistributed manner in the resin package 62; therefore, positions wherewater flocculates are distributed, whereby concentration of vaporpressure is reduced. This suppresses a rapture of the resin package 62in a test involving moisture absorption and heating, thereby enhancingthe reliability of the semiconductor device. FIGS. 17A to 17C show acase where the chip size of each IC element 51 is 2 mm per side, and inFIG. 17A, the resin package is not shown to avoid complication of thedrawing.

In the first embodiment, the copper plate 1 corresponds to a “metalplate” in the invention, the posts 40 to “metal posts,” the gold wires53 to a “conductive material,” and the metal thin film 9 to a “platedlayer.”

In the first embodiment, a case where the posts 40 are systematicallydisposed in the vertical and lateral directions in a plan view, that is,disposed in the form of a grid in a plan view, as shown in FIG. 16B, hasbeen described. However, the disposition of the posts 40 is not limitedto such disposition. For example, as shown in FIG. 18, the posts 40 maybe disposed in a manner that odd columns and even columns are displacedfrom each other by half pitch in a plan view, that is, may be disposedin a staggered manner in a plan view. Even with this configuration, theposts 40 can become any of die pads and outside terminals; therefore, nodedicated die pads are needed unlike in related art examples.

Also, in the first embodiment, a case has been described where theprocess of etching the copper plate 1 to form the posts 40 is performedin two stages, in one of which the copper plate 1 is etched from its topsurface and in the other of which the copper plate 1 is etched from itsundersurface. However, the number of stages of the etching process maybe reduced from two from one. Specifically, as shown in FIG. 19A, first,the metal thin film 9 made of Ag or the like is plated on the entiresurface of the copper plate 1, whose undersurface has no recesses formedthereon and is flat. Subsequently, the plated undersurface of the copperplate 1 is pressed against the top surface of the substrate 21 that iscoated with the adhesive 23 so that these surfaces adhere to each other.Then, as shown in FIG. 6B, the copper plate 1 is etched using resistpatterns (not shown) as masks until it is penetrated, so that themultiple posts 40 are formed. After the multiple posts 40 are formed ofthe copper plate 1, the resist patterns are eliminated, and then, asshown in FIG. 6C, the IC element 51 is mounted on the posts 40 in theIC-fixing region. Then, the pad terminal of the IC element 51 is coupledto the posts 40 in regions other than the IC-fixing region via the goldwires 53.

This method allows the number of stages of the etching process to bereduced from two to one, thereby reducing the time required tomanufacture the wiring board 50 and thus reducing the manufacturingcost. Note that in the method in FIGS. 19A to 19C, the metal thin film 9made of Ag or the like is not formed on the outer peripheries of theposts 40. Therefore, the area of each post 40 that is coated with themetal thin film 9 is smaller than that in a case where etching isperformed in two stages. Thus, if the undersurfaces of the posts 40 aresoldered to, for example, a motherboard or the like, the strength ofbonding between the posts 40 and the motherboard is conceivably reduced.

(2) Second Embodiment

In the above first embodiment, a case (that is, a single chip package)where only one chip of IC element 51 is disposed in the resin package62, as shown in FIGS. 17A to 17C, has been described. However, theinvention is not limited to such a configuration.

FIGS. 20A to 20C are drawings showing a configuration example of asemiconductor device 200 according to a second embodiment of theinvention. More specifically, FIGS. 20A and 20B are plan views showingthe configuration example of the semiconductor device 200, and FIG. 20Cis an end view taken along line X20-X′20 of FIG. 20B. In FIG. 20A, theresin 61 is not shown to avoid complication of the drawing. In FIGS. 20Ato 20C, components similar to those shown in FIGS. 1A to 19C are givenidentical reference numerals and will not be described in detail.

As shown in FIGS. 20A to 20C, two or more IC elements 51 may be disposedin the resin package 62 in this embodiment. Such IC elements 51 may bean identical type of IC elements or may be different types of ICelements that differ from one another in outside shape or pad terminalcount. As is understood from the drawings, a MCM in which multiple ICelements 51 are sealed in the state of bare chips by one resin package62 is also manufactured using a method similar to the above-mentionedembodiment.

As shown in FIG. 20A, first, two IC elements 51 are mounted on the posts40 in IC-fixing regions (die attach process). Next, the posts 40disposed in regions other than the IC-fixing regions and the padterminals of the IC elements 51 are coupled via the gold wires 53 or thelike (wire bonding process). Then, as shown in FIGS. 20B and 20C, the ICelements 51, the gold wires 53, and the posts 40 are sealed using athermosetting epoxy resin or the like (resin-sealing process).Subsequently, the resin 61 sealing the IC elements 51 is removed fromthe substrate (not shown), and is diced into individual resin packages62 so that two IC elements 51 are collectively included in an identicalpackage.

Thus, according to the method for manufacturing the semiconductor device200 according to the second embodiment, the posts 40 can become any ofdie pads and outside terminals. Therefore, there is no need forpreparing dedicated die pads or a lead frame, or a dedicated substrate(interposer, etc.) for each type of the IC element 51 when assembling asemiconductor device. This reduces the manufacturing cost. With regardto the configuration of the semiconductor device 200, the posts 40serving as die pads or outside terminals are disposed in a distributedmanner in the resin package 62, as in the first embodiment. Therefore,positions where water flocculates are distributed in the resin 62,whereby concentration of vapor pressure is reduced. This suppresses arapture of the resin package 62 in a test involving moisture absorptionand heating, thereby enhancing the reliability of the semiconductordevice.

In this embodiment, as shown in FIG. 20A, the posts 40 in regions otherthan the IC-fixing regions may be used as relay terminals for the goldwires 53. Specifically, a post 40 a coupled to the pad terminal of theIC element 51 via a gold wire 53 a may be coupled to another post 40 bvia a gold wire 53 b. According to this method, the pad terminal of theIC element 51 can be drawn out to an arbitrary position without changingthe positions in which the posts 40 are disposed. Therefore, the outsideterminals of the semiconductor device 200 can substantially be changed.As a result, for example, the general versatility of the wiring board 50shown in FIG. 7 is further enhanced. Also, as shown in FIG. 20A, boththe pad terminals of the IC elements 51 may be electrically coupled viathe gold wires 53 and the posts 40. According to this method,flexibility in design of the semiconductor device is further enhanced.

In the second embodiment, the gold wire 53 a corresponds to a “firstconductive material” in the invention, the post 40 a to a “third metalpost,” the gold wire 53 b to a “second conductive material,” and thepost 40 b to a “fourth metal post.”

1. A semiconductor device comprising: a plurality of metal posts eachhaving a first surface and a second surface facing a side opposite tothe first surface, the metal posts arranged in vertical and lateraldirections in a plan view, the metal posts including a first metal postand a second metal post; an integrated circuit element fixed to thefirst surface of the first metal post; a conductive material, theconductive material coupling the first surface of the second metal postand a pad terminal of the integrated circuit element, and the conductivematerial, wherein the second surfaces of the metal posts are exposedfrom the resin.
 2. The semiconductor device according to claim 1,wherein the first and second posts are all formed to have identicalshapes and identical sizes.
 3. The semiconductor device according toclaim 1, wherein a plated layer for solder joint is formed on the secondsurfaces of the metal posts.
 4. A wiring board to be used to fix anintegrated circuit element and draw a pad terminal of the integratedcircuit element to outside, the wiring board comprising: a substrate;and a plurality of metal posts arranged in vertical and lateraldirections in a plan view on the substrate, wherein the substrate andthe metal posts are bonded together via a type of adhesive that losesadhesion force thereof if the adhesive is subjected to a predeterminedprocess.
 5. The wiring board according to claim 4, wherein the metalposts are all formed to have identical shapes and identical sizes.